(a) Field of the Invention
Embodiments of the present invention relate generally to flat panel displays. a thin film transistor array panel and a manufacturing method thereof.
(b) Description of the Related Art
A liquid crystal display, which is a popular type of flat panel display, typically includes two display panels having electrodes, and a liquid crystal layer interposed between the two display panels. The display controls the amount of light transmitted by applying voltage to the electrodes, thus rearranging liquid crystal molecules of the liquid crystal layer.
One of the two display panels constituting the liquid crystal display is a thin film transistor (TFT) array panel. The thin film transistor array panel is used to independently drive each pixel in a liquid crystal display, an organic electro-luminescence (EL) display device, or the like.
The thin film transistor array panel includes a scanning signal line or a gate line transmitting a scanning signal, an image signal line or a data line transmitting an image signal, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, a gate insulating layer providing insulation by covering the gate line, and an interlayer insulating layer providing insulation by covering the thin film transistor and the data line.
Meanwhile, as display devices increase in size, the size of the thin film transistor array panel also increases. The increase in the size of the thin film transistor array panel increases the influence of static electricity generated during a manufacturing process. In order to reduce the influence of this static electricity, one of the odd-numbered data lines and one of the even-numbered data lines are connected to each other outside a display area, and a connection portion is then cut out. However, in this case, in an etching process for forming data lines, etching speed may vary as between data lines that are connected and data lines that are not connected, which results in a thickness difference in the lower layers of the data lines. This may compromise the performance of a thin film transistor of a thin film transistor array panel or compromise display quality, resulting in undesirable phenomena such as vertical lines or the like.
In order to prevent this difference in etching speed, all the wirings may be formed without being connected. In this case, the influence of static electricity increases, and the thin film transistor thus typically cannot undergo a quality test, therefore allowing a greater number of defects.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art.